The present invention relates to treating or cleaning the surface of a wafer in the form of a thin sheet having on its surface a layer of semiconductor material (e.g., silicon (Si) or silicon-germanium (SiGe)), such layer being termed a “useful layer”, and constituting a medium from which large quantities of components (e.g., integrated circuit cells or discrete devices) can be produced.
One known technique for fabricating such wafers is the Smart Cut® technique, which can be used to obtain an SOI (silicon on insulator) wafer, for example. An example of carrying out the SMART-CUT® technique applied to the production of SOI wafers is described in U.S. Pat. No. 5,374,564 or in the article by A. J. Auberton-Hervé et al entitled “Why Can Smart-Cut Change the Future of Microelectronics?”, Int Journal of High Speed Electronics and Systems, Vol 10, No 1, 2000, p 131-146. In general, the SMART-CUT® technique consists in implanting atomic species into an implantation zone beneath the face of a semiconductor wafer (e.g., Si or SiGe), in bringing the face of the wafer that has undergone implantation into intimate contact with a support substrate, and in cleaving the wafer at the implantation zone to transfer the portion of the wafer that is located between the implantation zone and the surface through which implantation has taken place onto the support substrate.
Thus, a structure (e.g., a SOI structure) is obtained having a layer that has been transferred onto one face of a support substrate. After cleavage and transfer, the surface of the transferred layer is treated to remove part of the thickness of the implanted layer and to reduce the roughness of the cleavage surface. Examples of such treatments are described in U.S. patent application US 2004/115905 and International patent application WO01/15215. Typically, the treatment comprises a polishing step followed by a cleaning step carried out prior to an optional final step of sacrificial oxidation and/or a smoothing heat treatment. The polishing step can reduce the root mean square (rms) roughness to less than 2.5 Angstroms (Å) (e.g., 2 Å rms) for a scan area (carried out using an atomic force microscope, for example) of 2 micrometers (μm) by 2 μm.
More precisely, in a first step, polishing comprises a chemical-mechanical polishing step employing a polishing plate associated with a polishing solution containing both an agent for chemically attacking the surface of the layer and abrasive particles for mechanically attacking the surface, and a washing step, generally using deionized water (DIW). Thereafter, a cleaning step is carried out, consisting in treating the wafers with cleaning solutions.
To clean the surfaces of wafers having a surface layer of semiconductor material, it is known to use a standard treatment known as “RCA” (because it was developed by Radio Corporation of America) and which comprises:                a first cleaning step using an SC1 solution (Standard Clean 1) (or APM, Ammonium-Hydrogen Peroxide Mixture); containing ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O);        a second cleaning step using an SC2 solution (Standard Clean 2) (or (HPM, Hydrochloric Peroxide Mixture); containing hydrochloric acid (HCl), hydrogen peroxide (H2O2), and deionized water.        
The first solution, SC1, generally comprises 5 parts by volume water (H2O), 1 part by volume 27% ammonium hydroxide (NH4OH), and 1 part by volume 30% hydrogen peroxide (H2O2) and is generally used in the temperature range of 50° C. to 80° C., is principally intended to remove particles isolated on the surface of the wafer and particles buried close to the surface, as well as to render the surface hydrophilic.
The second solution, SC2, generally used in the temperature range of 70° C. to 90° C., is principally intended to remove metallic contamination that has become deposited on the wafer surface, in particular by forming chlorides.
For thin structures, i.e., structures such as SOI structures having a semiconductor useful layer of thickness of less than about 1000 Å, “HF” defect densities have been observed in the final products (i.e., after final sacrificial oxidation) which exceed the acceptable limits. “HF” defects are defects in the active semiconductor layer of the SOI structure that extend from the surface of the layer right into the buried oxide layer; their presence can be revealed by a ring pattern after treating the SOI structure with hydrofluoric acid (HF). The HF defect density observed for certain wafers may be as high as 15 defects per square centimeter (cm2), while the recommended limit value is typically of the order of 0.5 defects per cm2, or even less than 0.1 defects per cm2.
HF defects are considered to be “destructive” defects for wafers, since they render them non viable (i.e., of unacceptable quality) for subsequent treatments, in particular for component formation. Thus, there is a need for cleaning procedures that reduce the number of HF defects in the final product.